1. Field of the Invention
The present invention relates to electronic packaging and methods of fabricating same. More particularly, the present invention relates to semiconductor chip packaging using a multilayer thin) film for chip attachment to a substrate.
2. Background and Related Art
Ever increasing industry demand for smaller and smaller electronic packages with low profile, higher area density and increasing number of input/output connections (I/Os) has led to increasing demand for the Chip Scale Package (CSP). Use of such packages may be found in small portable products, such as cellular phones, pagers, and the like. However, it is known that CSPs have somewhat limited applications because of the limited number of I/Os due to solder interconnect reliability constraints. As feature sizes of the semiconductor chip packages decrease, as in the case of CSPs, and the I/O connection count increases, so too will the number of chips packaged in a given area. This will increase the heat dissipated by each of the chips which will, in turn, increase the thermal mismatch stresses between chip and substrate, the latter of which will decrease the interconnect reliability of the package. Various efforts have been made in the prior art to address the thermal mismatch problem. In addition, various efforts have been made to improve interconnect reliability and reduce cost by, for example, fabricating CSPs at the wafer level. However, these efforts have not been totally successful and have involved relatively complex and costly assemblies with limited capability.
In view of the limitations of prior art chip packaging mentioned hereinabove, there continues a need for a relatively simple, low profile, high density, chip packaging approach which has high interconnect reliability and high I/O connection count, and which may use relatively low-cost wafer scale processing.
In accordance with the principles of the present invention, a relatively simple chip packaging approach is provided using multilayer thin film technology. The flexible thin film acts as both a redistribution layer and a stress relief layer between chip and second level interconnect substrate. More particularly, the flexible multilayer thin film acts to provide multiple layers of redistribution metallurgy for both power and signals in the X-Y plane (e.g. fanout or grid change) and also provides sufficient flexibility to connections in both the Z-direction and X-Y plane to relieve stresses caused by the thermal expansion mismatch between semiconductor chip and second level interconnect substrate, such as, a PCB.
The flexible multilayer thin film is first mounted on either a silicon die or wafer. The upper surface of the thin film has an array of pads matching the array of pads on the die or wafer while the lower surface has pads matching those of the second level interconnect substrate. The mounting of the multilayer thin film on a die creates a module for mounting to the second level substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the modules.
Accordingly, it is an object of the present invention to provide an improved semiconductor chip package and method for making same.
It is a further object of the present invention to provide a chip package having a flexible multilayer redistribution thin film attached thereto to form a low profile, low vertical inductance, module.
It is yet a further object of the present invention to provide a chip module comprising a flexible multilayer thin film attached to the chip which thin film acts as both a redistribution medium and stress relief medium between chip and next level of packaging.
It is another object of the present invention to provide a chip module formed by fabricating a flexible multilayer redistribution thin film on a wafer before dicing.
It is yet another object of the present invention to provide a chip package and method of making same which acts to increase interconnection reliability and I/O count and provide simple, low cost, assembly.
These foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings, wherein like reference members represent like parts of the invention.